Both data processing and digital communication switching systems send data over communication lines to a system processor. In data processing systems, data is transmitted between a plurality of terminal devices and the processor for processing. In communication switching systems, data is transmitted between telephones, or other terminal devices, and the switch processor for call control purposes.
In each type of system, data can be sent over a plurality of lines in the HDLC format to the processor. Each line terminates at the processor end in an interface or port which interfaces the communication line to the processor. In data processing systems, the number of lines is often small (100 or less), relative to intermediate or large sized communication systems, and the cost of the terminal devices is relatively high ($1000 or more). Thus, the cost of the ports that terminate each line can be relatively expensive without unduly increasing system costs. The message traffic per line can be relatively high because fewer lines connect to the processor. Also, since the typical data processing system has a hundred lines or less, the communication line interface circuitry is relatively compact physically. For this reason, it is common practice to support the HDLC protocol of the communication line in the receiving port and to transmit the data portion of each HDLC frame to the processor without protocol support. This can be done with a sufficiently low error rate because of the relatively dense physical system configuration and the resulting close proximity of the processor to all ports.
Conditions are otherwise in communication switching systems. These systems have a large number of lines (often a thousand or more), they have less traffic per line and the telephones or other terminal devices are relatively inexpensive. Since there are a large number of lines, the cost of the ports that terminate each line is an important factor in keeping the cost per line and the cost of the overall system low.
The typical communication switching system is physically larger than the typical data processing system because of the large number of lines and associated ports. This results in the system processor being a significant distance from the ports. One advantage of the HDLC protocol is its capability to recover from transmission errors. If the HDLC protocol support occurred in the port, its error correction capabilities would not extend to the processor. Therefore, it is desirable to extend the protocol through to the processor in communication switching systems in order to maintain a satisfactorily low data error rate. Also, the function of receiving incoming messages at the ports and transmitting them to the processor must be performed efficiently so as not to burden the real time capabilities of the processor.
In prior art arangements, the communication paths extending from the terminals to the ports transmitted data using the HDLC protocol with each path being terminated by an HDLC formatter chip and a microprocessor within the associated port. The formatter and microprocessor supported the HDLC protocol of each path. The formatter chip performed the conventional functions such as flag detection, flag generation, zero insertion, zero deletion, CRC calculation, serial to parallel conversion in the receiving direction, and parallel to serial conversion in the transmitting direction. The formatter chip supplied the message bytes, one at a time, to the microprocessor which stored the bytes until a complete message was received. The microprocessor supported the procedural aspects of the HDLC protocol such as error control, channel initialization and flow control. The microprocessor buffered each frame before sending it to the system processor.
The above-described arrangement is not totally satisfactory for a number of reasons. First of all it requires a microprocessor per port. This represents a significant increase in system costs in a system having thousands of ports. The above arrangement is also less than ideal since the protocol is terminated before the message information arrives at the system processor. This means that the error recovery and flow control capabilities of the protocol do not function between the port and the processor. While this arrangement reduces the real time burden on the processor, it increases the probability of error since the transmission to the processor does not include the error control mechanisms of a protocol.
A system having a thousand or more ports can be physically large so that there is a significant distance between any one port and the system processor. The probability of error in transmission between a port and the processor is therefore high. Another protocol could be implemented between the ports and the processor to solve this problem, but this would create additional expense and system complexity.
The goal of maintaining HDLC support through to the processor and the goal of minimizing the real time burden on the processor are conflicting. It would be easy to provide a system in which the port sends the entirety of each message, including the protocol support data, through to the processor. This would minimize data errors but would unduly burden the processor with needless work and would limit its real time capability. On the other hand, there are systems in which all protocol information is deleted at the port so that only the data message is sent to the processor. This minimizes the real time burden on the processor, but results in excessive data error rates in large systems due to noise, etc. on the paths connecting the ports and the processor.
It is therefore a problem to provide an economical system in which the terminal data on a plurality of HDLC communication lines are passed by the receiving ports to the processor by expedients which minimize the required processor real time burden but which also provides enough protocol support to minimize data errors.